
Release notes for Marvell CORE Driver, release: 3.6.1
============================================================================

Table of Contents
-----------------

1.	Contents of Release
2.	Changes from Previous Releases
3.	File Structures
4.	Known Issues
5.      Notes
6.      Disclaimer
	

1. Contents of Release 3.6.1
==============================

 - Support for 88SX50XX adapters stepping B0 and B2.

 - Support for 88SX60X1 adapters stepping B2 and C0.

 - Support for 88SX6042 adapters.
 
 - Support for 88SX7042 adapters.

 - Support for Fis Based Switching mode and 128 EDMA entries mode.

2. Changes from Previous Releases
=================================
Changes from Release 3.4.9
--------------------------
Updated files:
mvStorageDev.c
mvSata.h
mvSata.c
mvRegs.h

Added new generation "GEN_IIE" for the 6042 and 7042 adapters.

Added pre-compiler sanity checks in mvSata.h.

Added new enumeration for the switching modes.

Support the EDMA single region feature.

Added ability to remove the MV_QUEUE_COMMAND_INFO structure from the 
CoreDriver's command entry data structure and to have only a pointer to that 
structure. This is to reduce significantly the size of the statice memory allocated
by the CoreDriver. To enable this mode, the IAL must define the 
MV_SATA_STORE_COMMANDS_INFO_ON_IAL_STACK macro, and not to free the memory allocated 
for the MV_QUEUE_COMMAND_INFO structure when calling mvSataQueueCommand()
as long as the command is note completed by the CoreDriver.

Using one commands array for all channels of an adapter (this array 
allocated in the adapter data structure). Removed the commands array from
the channel data structure.

Remove the decliration of internal functions used for debug purpose from 
mvSata.h

Renamed the NCQErrHandlingInfo field (part of the channel structure) to 
ErrorHandlingInfo.

Added defines for register address of the PCI-Express unit.

In unmaskEdmaInterrupts(), clear the Serror and FIS interrupt cause registers
before clearing EDMA error cause.

Added pointer to the command info strucutre in the command entry structure.

In handleEdmaFailedCommand(), get the command tag from the ATA shadow registres
in TCQ mode.

Moved the code that hanldes PCI error interrupts from the ISR function to new
internal function handlePCIErrorInterrupt().

In isGoodCompletionsExpected(), added check for new entries in the response queue
when in NCQ mode.

In getHostTagByDeviceTag(), remove the special handling of the 32 entries mode.

Enabled the following features of the EDMA in GEN_IIE adapters:
early completion, host queue cache, cutthrough.

Fixed mvSataSetChannelPhyParams(); clear bit 16 when writing to PHY mode 2 
register.

Added the MV_NO_SW_RESET_FOR_THE_ADAPTER define to disable the global software
reset sequence.

Modified the TCQ Error handling flow; when there is only one outstanding command,
then that command will be marked as the erring command. Otherwsize, the erring
command will be identified according to the device tag from the ATA Sector
Count register.

The TxAmp and TxPre are set to 7 and 1 (respectively) when the is no serial eprom
initialization.

Added the 88SX60X1 FEr SATA #25 workaround.

Modified the disconnect interrupt handling; if the link indication still exists
then report unrecoverable HW error.

Added support for Serial ATA phy layer power management.

Rename the implementXXXXWorkarounds fields of the MV_SATA_ADAPTER to chipIsXXXX.

Added support for the FBS mode.
Added support for the 128 EDMA entries mode.
 
In mvRegs.h, Added registers and defines needed for FBS and 128 EDMA entries
mode.

Added new API function mvSataSetFBSMode(), This function called by the IAL to
enable or disable the FBS and 128 EDMA entries features.

Added new API define called MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN, If this macro
defined by the IAL, then the CoreDriver allows up to 127 commands to be queued 
to a channel when the 128 EDMA entries mode is enabled. 

Added new API defines that enables the IAL to configure the CoreDriver's queue 
size for a channel when the 128 EDMA entries mode is enabled. Those defines are:
1. MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN - when defined by the IAL, The CoreDriver
   uses MV_SATA_GEN2E_SW_QUEUE_SIZE as the queue size in the 128 EDMA entries
   mode. The default value of MV_SATA_GEN2E_SW_QUEUE_SIZE is 127.

2. MV_SATA_OVERRIDE_GEN2E_SW_QUEUE_SIZE - when defined by the IAL, The
   CoreDriver set MV_SATA_GEN2E_SW_QUEUE_SIZE to MV_SATA_REQUESTED_GEN2E_SW_QUEUE_SIZE

3. MV_EDMA_GEN2E_REQUEST_QUEUE_SIZE - defined by the CoreDriver, holds the EDMA
   request queue size (in bytes) for a channel when the 128 EDMA entries mode is enabled.
   
4. MV_EDMA_GEN2E_RESPONSE_QUEUE_SIZE - defined by the CoreDriver, holds the EDMA
   response queue size (in bytes) for a channel when the 128 EDMA entries mode 
   is enabled.

Removed the commandTag from the command context data structure, instead added 2
tags, one for the host (0-127) and one for the device (0-31).

Added new data structure for handling the host and devices tags, the new data 
structure includes tags stacks, one for the host and one for each device.

Using one error handling data structure and error handling state machine for NCQ,
TCQ and normal (none queued) modes when FBS is enabled.

Remove the "NCQ" term from the NCQ error handling data types as now it used for
none NCQ modes too.

Moved the decliration of internal functions used for debug purpose from mvSata.c
to mvSata.h, so those functions can be use outside the CoreDriver, this change
may be removed in the future releases.

Added new internal functions:
1. _setRegBits - set given bits in 32 bit register.
2. _clearRegBits - clear given bits in 32 bit register.
3. setupEdmaDeviceErrorHandlingConfiguration - configures the EDMA registers that
   relevant to the ATA device errors according to the selected EDMA and switching
   mode.
4. _getHostTagByDeviceTag - finds the host tag by the device tag and the device
   number.
5. writeGen2EEdmaRequestEntry - populates EDMA request for GEN_IIE adapter.

In handleEdmaFailedCommand(), reslove the device tag of the failed command from
the ATA shadow registers instead of the EDMA status.

In handleEdmaResponse(), ignore bit 5 (Serror) in the response flags, and bit 2
(Device Error) in NCQ mode.

In handleEdmaInterrupt(), update pSataChannel->rspOutPtr before calling 
handleEdmaResponse(), since the later function may update this variable.

In handleRecoverableError(), clear SError bit in the EDMA error cause after
clearing SError reg.

In handleAsyncNotify(), clear FISInterruptCause register then clear bit 8 in the
 EDMA error cause.

clearing the "recoverable errors counter" when doing reset to the channel.

In mvSataConfigEdmaMode(), for the GEN_IIE adapters, override the hardware
default value of RX PM port mask to be disabled.

In _dumpEDMARegs(), added some of the new registers of the GEN_IIE adapters.

In dumpAtaDeviceRegisters(), for the GEN_IIE adapters, enabled the access
ro the ATA device registers even when the EDMA is enabled.

Changes from Release 3.4.8 (Internal release)
---------------------------------------------
Updated files:
mvSata.c

Fixed _channelHardReset, added delay of 1 mseconds for H1 devices after reset.

In handleEdmaInterrupt(), check only bits 3 and 4 in the sanity check of the
EDMA error cause register after the register cleanup (instead of checking
all bits).

Changes from Release 3.4.7 (Part of Linux 3.4.0 release)
--------------------------------------------------------
Updated files:
mvSata.h
mvSata.c

Removed support for 88SX60X1 adapters stepping B1.

Workarounds that are not relevant to 88SX60X1 stepping C0 are activated only
to 88SX60X1 B2.

Fixed 60X1 FEr SATA #23; in the previous implementation, the register PhyMode2
is updated when the AtaRst bit is set. In this revision, the update was
moved into the _fixPhyParams() function which is called after AtaRst bit
is cleared.

For the 60X1 adapters, when writing to PhyMode2 (for example while updating the
PRE/AMP values) bit 16 must be zero.


Changes from Release 3.4.0
----------------------------
Updated files:

Move compiler dependent includes from mvLog.c to mvOs.h. These includes are:
stdio.h and stdarg.h

In mvRegs.h, masked bit 5 in the Gen II EDMA error mask, and added it to the
recoverable EDMA errors mask

In mvSata.c remove an unused function mvAta2HostString() and added initialization
to local variables to prevent compiler warnings.

In handleRecoverableError() function, clear the SError register if bit 5 is set in
the EDMA error cause.

In mvSataConfigureChannel, disable SaDevInterrupt(). The interrupt is enabled only
when enabling the commands queuing.

Added files:


Deleted files:


Changes from Release 3.2.1
----------------------------
Updated files:

Added NCQ and queued command based switching support (Marvell port multipliers).
The NCQ supports is configuring EDMA in NCQ mode and error handling in case
device error in NCQ / queued command based switching.
The error handling is sending READ LOG EXT page 10 command to the failed drive;
the allocation of the response buffer of this command is put in the request
queue in order to save space.
The algorithm is as follows -
If device error is detected continue sending and executing commands in request
queue and modify the state of the channel to NCQ error handling.
In this state the driver waits for all commands on the other drives to complete
(if any) and afterwards it issues EDMA disable and sends the READ LOG EXT SATA
command.
The errorneous command is completed to the IAL with the corresponding error
condition and the abort commands (commands that are queued after the error
occured and commands that are aborted by the drive) are requeued to the EDMA
to continue command execution.

Added fatal error debug prints. This is in order to add prints of debug messages
of fatal events (such as invalid pointers etc...)

Added 88SX60X1 FEr SATA #16 workaround.

Added support for recovered / unrecovered errors event notification call back.
Upon such event the IAL is called with the event notification function.
If there was 10 consecutive recovered errors with no DMA or PIO operation
completed, then the IAL notification function is called with unrecovered
error notification.
The recover / unrecovered errors are detected from the EDMA error cause
register.
This new mechanism is described in a companion document for the release
explaining the differences between CORE driver version 3.2.1 and 3.4.0

Added support of modifying the DRQ block size (instead of fixed 512B). This
can be done by modifying the variable DRQDataBlockSize in the channel's
data structure.

Added a sanity check in dumpAtaDeviceRegisters to check if EDMA is active
or not. If not then the function will not dump the ATA registers.

Added FUA boolean field in MV_UDMA_COMMAND_PARAMS struct. This feature is used
only with NCQ drives and used to direct the hard drive to perform the required
IO bypassing the drive's cache buffers.

Added MV_ERROR_HANDLING_STATE struct the describes NCQ error handling
state machine used by the CORE driver per SATA channel.

Removed 88SX50XX B1 support. The supported device of 88SX50XX are B0 and B2
stepping (note that future revision support feature is still implemented)

Removed 88SX60X1 A0 and B0 support. The supported devices of 88SX60X1 are
B1 and B2 stepping (note that future revision support feature is still implemented).

Removed auto flush mechanism. Instead a fixed mechanism of re-queuing the
aborted commands after device error algorithm is performed.

Modified fix for 88SX60X1 FEr SATA #10 to retry OOB sequence in case the
SStatus after OOB is not 0x0 or 0x123 or 0x113.

Removed the code that sends SW reset to the hard drive after device error
in case of 88SX60X1 device.
Instead SW reset is sent to 88SX60X1 device when activating EDMA when BSY is
'1' OR DRDY is '0' OR DRQ is '1'.
Note that the driver sends SW reset in the 88SX50XX adapter after device
error condition.

When sending vendor unique FIS using 'sendVendorUniqueFIS' function, perform
polling of 1uSec intervals instead of 10uSec. This decreases the execution
time of this function since the FIS is likely to be sent in less than the
interval polling time.

Added a call to disable SaDevInterrupt in mvSataConfigureChannel. The
device interrupts in PIO command will be enabled when queuing a PIO command
through mvSataQueueCommand.


Added files:


Deleted files:



Changes from Release 3.2.0-B
----------------------------
Updated files:

Modified log messages

Added dump of SATA register in handleEdmaFailedCommand.

In handleEdmaInterrupt read the EDMA error cause as 32bit register and not 16bit.
This modifications is to support extra bits added to 88SX60X1 adapters.

In handleEdmaInterrupt add workaround to wait extra 20mSec after clearing EDMA error
cause register in case the register is set back again. This is in order to workaround
a port multiplier's hotplug on device SATA channels issue.

In handleEdmaInterrupt add prints of PCI and EDMA registers in case a parity error
is detected.

In handleEdmaInterrupt in the disconnect handler, when receiving such event and the link
is still up then don't send a disconnect event notification.
Such scenario is found when using hot plugging port multiplier and it is in legacy mode.

In handleEdmaInterrupt in the connect handler, when receiving such event and the link
is down then don't send a connect event notification.
Such scenario is found when using hot plugging port multiplier and it is in legacy mode.

In handleEdmaInterrupt added a fix not check SATA interface status when the adapter
is 60X1 A1 stepping.

For 50X1 in handleEdmaInterrupt connect handler, if a connect is received then issue
COMRESET twice to the drive. This is in order to fix hot plug issue with non-marvell driven
hard drives.

In _establishSataComm modified the timing between the issue of DET 1 and 0 to the SControl
register.
Also added a code to wait up to 200mSec for checking if PHY is ready.

In activateEdma when clearing EDMA interrupts for 60X1 devices, the code doesn't clear
bit 8. This is in order to keep previous SDB FIS sent by port multiplier upon hot-plug event
on it's device side SATA channels.

Modified pre/amp parameters for 60X1 B0 adapter to 2 and 6 respectivly.

Added fix for 88SX60x1 FEr PCI#7.

Removed unneeded delay in checkSStatusAfterHReset.
Also the SStatus check is performed also on 50XX adapter.

Added setting for EDMA command threshold to 0x4b when configuring EDMA in NCQ mode.

Removed semaphores in mvSataCheckPendingInterrupt.

In mvSataInterruptServiceRoutine, when receiving a PCI error then print the PCI and all
EDMA registers.

Modified default log function to printf.

In executeNonUDMACommand if the command is for port multiplier's internal register then
don't check the ATA Status if ready.

In mvPMDevEnableStaggeredSpinUpAll poll for 200mSec and wait for DET 3 or DET 0.



 Added files:


 Deleted files:


3. File Structures
==================

-->CoreDriver
      |
      +----->mvSata.c
      +----->mvSata.h
      +----->mvStorageDev.c
      +----->mvStorageDev.h
      +----->mvRegs.h
      +----->mvLog.c
      ------>mvLog.h

4. Known Issues
===============

5. Notes
========
For the 60X1 stepping C0, the Serror interrupt bit 5 (error reporting feature)
in the EDMA error cause register is not enabled.

When using CORE driver version 3.4.x, the IAL must be modified according
to ../docs/COREModifications_3_2_1_to_3_4_0.pdf

6. Disclaimer
=============
No part of this document may be reproduced or transmitted in any form or by any means,
electronic or mechanical, including photocopying and recording, for any purpose, without
the express written permission of Marvell. Marvell retains the right to make changes to
this document at any time, without notice. Marvell makes no warranty of any kind,
expressed or implied, with regard to any information contained in this document,
including, but not limited to, the implied warranties of merchantability or fitness for
any particular purpose. Further, Marvell does not warrant the accuracy or completeness
of the information, text, graphics, or other items contained within this document.
Marvell products are not designed for use in life-support equipment or applications that
would cause a life-threatening situation if any such products failed. Do not use Marvell
products in these types of equipment or applications.
Marvell assumes no responsibility, either for use of these products or for any infringements
of patents and trademarks, or other rights of third parties resulting from its use. No
license is granted under any patents, patent rights, or trademarks of Marvell.
These products may include one or more optional functions. The user has the choice of
implementing any particular optional function. Should the user choose to implement any of
these optional functions, it is possible that the use could be subject to third party
intellectual property rights. Marvell recommends that the user investigate whether third party
intellectual property rights are relevant to the intended use of these products and obtain
licenses as appropriate under relevant intellectual property rights.
With respect to the products described herein, the user or recipient, in the absence of
appropriate U.S. government authorization, agrees:
1) Not to re-export or release any such information consisting of technology, software or source
code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to
a national of EAR Country Groups D:1 or E:2;
2) Not to export the direct product of such technology or such software, to EAR Country Groups
D:1 or E:2, if such technology or software and direct products thereof are controlled for national
security reasons by the EAR; and,
3) In the case of technology controlled for national security reasons under the EAR where the direct
product of the technology is a complete plant or component of a plant, not to export to EAR Country
Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct
product is controlled for national security reasons by the EAR, or is subject to controls under the
U.S. Munitions List ("USML").
At all times hereunder, the recipient of any such information agrees that they shall be deemed to have
manually signed this document in connection with their receipt of any such information.
Copyright  2004. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo,
Moving Forward Faster, Alaska, Fastwriter, GalNet, PHYAdvantage and Prestera are registered trademarks of
Marvell. Discovery, DSP Switcher, GalTis, Horizon, Libertas, Link Street, NetGX, RADLAN, Raising The
Technology Bar, The Technology Within, UniMAC, Virtual Cable Tester, and Yukon are trademarks of Marvell.
All other trademarks are the property of their respective owners.
